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AXIS ETRAX 100LX

Multiple device interfaces, Ethernet controller and a variety of memory options

Designed to meet demands for low cost, easy implementation and superior network performance, the ETRAX 100LX is Axis' sixth-generation optimized system-on-a-chip solution for putting peripherals on the network. The ETRAX 100LX was developed using 0.25µm ASIC technology.

Competitive price/performance ratio

The ETRAX 100LX with a powerful CPU, MMU (Memory Management Unit), integrated Ethernet (10/100), and many device interfaces, is a price competitive hardware option for designers of embedded Linux appliances such as Internet gateways, access control equipment, industry automation controllers, Bluetooth^TM appliances etc. Combined with the latest available Linux kernel, and the strong support and design help provided by Axis' engineers, product development teams are able to quickly get to market with competitive products.

Summary of ETRAX 100LX specifications

• CPU: 100 MIPS 32-bit RISC design with MMU and 8KB on-chip cache
  
  
• Memory controller: supports 4 GB of address SDRAM, EDO DRAM, SRAM, EPROM, EEPROM, Flash PROM without external logic
  
  
• System controllers:
  
  
  • Internal 100 MHz system clock generator; uses 20 MHz external crystal
    
  • 10 DMA channels
    
  • Vectorized interrupt controller
    
  • 2 8-bit timers with programmable clock
    
  • Watchdog timer (dedicated)
  
  
• I/O Ports:
  
  
  • Ethernet: 10/100 megabit data rate, full duplex
    
  • 4 high speed asynchronous serial ports
    
  • 2 high speed synchronous serial ports
    
  • 2 USB 1.1 Host/Device ports
    
  • 2 IEEE=1284 (ECP/EPP) bidirectional parallel ports
    
  • SCSI: Initiator (host) mode controller, supports synchronous, asynchronous, SCSI-3, Fast-20, ...
    
  • EIDE/ATA-2 ports: configurable for up to 4 (multiplexed with pins for SCSI, parallel port, and 2 serial ports)
    
  • Two 8-bit general purpose I/O ports with configurable pins
  
  
• Bootstrap program download: support for initial loading to internal cache memory from parallel port, serial port, and network; code, loaded to cache, can be designed to enable download of program to initially empty Flash PROM or other external memory.